Mô tả công việc
About the Role
We are looking for a senior verification engineer to work on high‑speed mixed‑signal PHY IP that powers memory and interconnect infrastructure in AI, data center, and next‑generation compute chips.
What You’ll Be Doing
- Develop and execute verification plans for high‑speed mixed‑signal PHY IPs, defining coverage goals, test scenarios, and success criteria.
- Perform RTL simulations and gate‑level SDF‑annotated simulations within UVM‑based verification environments.
- Build functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocks.
- Generate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumption.
- Debug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causes.
- Collaborate with design, analog, and integration teams to align verification strategy with IP architecture.
- Review and refine verification infrastructure, identifying coverage gaps and proposing new tests to close them.
The Impact You Will Have
- Catch critical bugs before tapeout, preventing costly respins and protecting customer schedules.
- Enable faster time‑to‑market for Synopsys PHY IP by delivering verified, production‑ready blocks.
- Improve verification quality across the team by building reusable test components and coverage models.
- Provide early feedback to design teams on corner cases, timing issues, and power anomalies.
- Support successful customer integrations by ensuring PHY IP works reliably across process corners and voltage ranges.
- Strengthen the verification foundation for next‑generation PHY products including DDR, HBM, and UCIe.
- Reduce post‑silicon debug cycles by catching gate‑level and power issues during simulation.
What You’ll Need
- 5+ years of hands‑on experience in ASIC RTL design flow with a strong focus on verification and debugging.
- Demonstrated expertise in RTL and gate‑level simulation, including SDF‑annotated GLS.
- Proficiency in SystemVerilog and experience working within UVM‑based verification environments.
- Strong debugging skills across waveform analysis, coverage review, and simulation log interpretation.
- Experience with power analysis tools such as PrimeTime PX, including VCD generation.
- Knowledge of high‑speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plus.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
Who You Are
- You can look at a failing gate‑level simulation and zero in on the signals that matter, then explain what broke and why without needing slides.
- You treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gaps.
- You communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precision.
- You stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixes.
- You are comfortable working in English across global teams, writing clear bug reports and participating in technical discussions.
The Team
You will join a Digital Design team focused on developing high‑speed mixed‑signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer‑facing engineers to deliver production‑ready IP blocks.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Diversity and Inclusion
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.