Mô tả công việc
Your role
- Be responsible for the verification of digital designs.
- Be able to understand requirements & specifications.
- Focus on Test plan and test bench development.
- Be responsible for IP verification (Formal, SystemVerilog, UVM).
- Support the Flow & Methodology improvements.
Your profile
- Degree in Electronic or Computer Engineering.
- 0-3 years of industry experience in Digital Verification.
- Development of verification environments and methodologies at block subsystem level.
- Extensive knowledge of SystemVerilog / Verilog / UVM / VMM.
- Fluency in English.