Mô tả công việc
Job Summary
We are seeking a Digital Verification Engineer who will champion the verification of digital designs, grasp requirements and specifications, and lead the development of test plans and test benches.
Responsibilities
- Be responsible for the verification of digital designs.
- Understand requirements & specifications.
- Focus on test plan and test bench development.
- Be responsible for IP verification (Formal, SystemVerilog, UVM).
- Support the flow & methodology improvements.
Qualifications
- Degree in Electronic or Computer Engineering.
- 0‑3 years of industry experience in Digital Verification.
- Development of verification environments and methodologies at block subsystem level.
- Extensive knowledge of SystemVerilog / Verilog / UVM / VMM.
- Fluency in English.