Mô tả công việc
Position Summary
We are seeking an experienced and detail-oriented Physical Design Engineer to join our Advanced ASIC/SoC Development Team. In this role, you will be responsible for the complete RTL‑to‑GDSII physical implementation of high‑performance, complex digital integrated circuits (ICs) built on advanced technology nodes (e.g., 7 nm, 5 nm, or below). You will collaborate closely with RTL design, architecture, DFT, and CAD team members to deliver power, performance, and area (PPA) optimized silicon on aggressive timelines.
Responsibilities
- Design Implementation: Execute physical design from RTL to GDS on advanced technology of 5 nm and below.
- Timing and Power Integrity Closure: Perform static timing analysis, ensure power integrity, and meet IR drop criteria.
- Physical Verification: Close DRC, LVS, ERC, and ANT.
- Collaboration: Work with the global engineering team to deliver design, ensuring design quality.
Requirements
- Education: BS, MS in Electrical Engineering, Electronics Engineering.
- Minimum of 3 years of hands‑on experience in physical design engineering for complex integrated circuits.
- Proficiency in Synopsys (ICC2, Fusion Compiler, PrimeTime) or Cadence (Innovus, Genus).
- Scripting languages: strong skills in Tcl, Python, and Perl.
- Experience with advanced processes.