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Job Summary
We are looking for a Senior Staff Engineer in Digital Design to develop high‑speed mixed‑signal PHY IP blocks in SystemVerilog and Verilog. The role involves writing clean, synthesizable RTL, authoring micro‑architecture specifications, and ensuring design quality through linting, CDC checks, and coding standards.
Responsibilities
- Design and develop high‑speed mixed‑signal PHY IP blocks in SystemVerilog and Verilog.
- Author detailed micro‑architecture specifications based on industry protocol standards.
- Execute RTL design from concept through tape‑out, ensuring design quality through linting, CDC checks, and adherence to coding standards.
- Collaborate with verification engineers to debug and resolve issues in RTL simulations and gate‑level simulations with SDF timing annotation.
- Provide technical support to customers during SoC integration, post‑silicon bring‑up, and field deployment.
- Participate in design reviews and mentor junior engineers on RTL best practices.
Impact
- Your RTL designs will power high‑speed connectivity IP used in customer SoCs across automotive, mobile, and data‑center applications.
- Micro‑architecture decisions will determine whether customer integrations succeed on schedule or require costly respins.
- Collaboration with verification will reduce bug escape rates and improve IP quality metrics that directly affect revenue.
- Technical support will keep customer programs on track, preventing delays that could cost millions in lost market opportunity.
- Design quality and documentation will enable faster reuse across product lines, reducing time‑to‑market for future IP releases.
- Methodologies built will improve team productivity and reduce manual effort in future tape‑outs.
Requirements
- 5+ years of hands‑on experience in ASIC RTL design flow, from specification through tape‑out.
- Strong proficiency in SystemVerilog and Verilog for complex digital design.
- Experience with scripting languages such as Python, Perl, or Tcl for design automation.
- Solid understanding of design quality checks including linting, CDC analysis, and synthesis constraints.
- Strong English communication skills for cross‑functional collaboration and customer interaction.
- Experience with post‑silicon debugging and customer support is a strong plus.
- Knowledge of high‑speed serial protocols, DFT techniques, or UVM verification methodologies is a plus.
Who You Are
- You can explain a complex timing closure issue to a customer engineer in two sentences without losing technical nuance.
- When verification flags an issue late on Friday, you dig in to understand root cause rather than applying a quick fix.
- You write RTL comments and specs assuming the next person reading them will be you in six months.
- You push back when a protocol requirement is ambiguous or a design decision will create downstream problems, and you do it constructively.
- You are organized enough to manage multiple IP blocks at different stages while keeping quality high across all of them.
Team
You will join the Digital Design team within Synopsys IP Group, working on high‑speed mixed‑signal PHY IP development. The team operates across Ha Nội, Da Nang, and Ho Chi Minh City, collaborating closely with verification, analog design, and customer support teams globally.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Diversity Statement
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.