Mô tả công việc
Job Description
Senior Designer
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Job Summary
We are seeking a Physical Design Engineer responsible for executing and owning the RTL‑to‑GDSII implementation flow for ASIC/SoC designs. The role includes floorplanning, place & route, timing closure, power integrity, and physical verification, ensuring high‑quality, tape‑out‑ready silicon.
Key Responsibilities
- Execute complete RTL / Gate‑level Netlist to GDSII flow for blocks or full chip.
- Ownership of physical implementation of design partitions/blocks. Responsible for delivering timing clean blocks that meet sign‑off targets including DRC, LVS & IR closure for tape‑out readiness.
- Floor planning & Power Planning
- Timing Closure & STA
- CTS & Signal Integrity
- Physical Verification & Sign‑off
Skill Requirements
Technical Skills
EDA Tools
- Place & Route:
- Cadence Innovus
- Synopsys IC Compiler II / Fusion Compiler
- Timing & Power:
- PrimeTime, Tempus
- Voltus / PowerReplay
- Physical Verification:
- Calibre / Pegasus / IC Validator
Flows & Knowledge
- RTL / Netlist‑to‑GDSII
- Multi‑Vt / Multi‑Voltage designs
- Low power (UPF / COPF)
- DFT‑aware physical implementation
- Advanced nodes (28nm → 3nm preferred)
Programming/Scripting
- Proficiency in Python/Perl/Shell scripting for automation
Other Requirements
Education
- B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent
- 2-5 years of experience
Soft Skills
- Strong analytical and debugging skills
- Good communication and cross-functional collaboration
Information at a Glance
Yêu cầu kinh nghiệm
B.Tech/M.Tech in Electronics, Electrical, or Computer Engineering; 2-5 years experience; proficiency in EDA tools (Innovus, IC Compiler II, PrimeTime, Calibre) and Python/Perl/Shell scripting.