Mô tả công việc
Job Description
Senior Developer
| Hanoi, Hà Nội, thủ đôHo Chin Minh, Hồ Chí Minh, thành phố [Sài Gòn]
Job Summary
Perform end‑to‑end physical design flow:
- Floorplanning
- Power planning (PG grid, IR)
- Placement & optimization
- CTS (Clock Tree Synthesis)
- Routing
Key Responsibilities
- Post‑route optimization
- Achieve timing closure across all modes and corners
- Resolve DRC, LVS, ERC and signoff violations
- Handle low‑power design techniques:
- Multi‑Vt, Multi‑voltage (UPF)
- Power gating, clock gating
- Perform physical verification and signoff
Skill Requirements
- STA (Primetime)
- SI / Crosstalk
- IR drop & EM analysis
- Work on advanced nodes (7nm, 5nm, 3nm or below)
- Collaborate with:
- RTL & Micro‑architecture teams
Other Requirements
- DFT & Test engineers
- Foundry and CAD teams
- Debug complex timing, congestion, power, and variability issues
- Drive methodology improvements and automation (scripts/flows)
1.5 to 3.5 years of industry experience
Information at a Glance
Yêu cầu kinh nghiệm
1.5 to 3.5 years of industry experience in physical design, timing closure, DRC/LVS/ERC resolution, low‑power design, and advanced node (7nm, 5nm, 3nm) work.